Temperature stabilized voltage reference circuit

ABSTRACT

Each of a pair of PN junction diodes (D 1  ; D 2 ) is separately dynamically biased by a different clocked current source arrangement (C 1 , M 2  ; C 2 , M 5 ). The resulting diode voltage drops (V 1  and V 2 ) are fed through a weighted difference amplifier (A; C 3 , C 4 , C 5 , C 6 ) to produce a voltage reference V OUT  which is relatively insensitive to temperature variations of the semiconductor body in which the PN junction diodes are integrated.

FIELD OF THE INVENTION

This invention relates to the field of semiconductor apparatus, and moreparticularly to MOS (metal oxide semiconductor) voltage referencecircuits.

BACKGROUND OF THE INVENTION

Semiconductor integrated circuits often require a voltage supply circuitor voltage "reference" for providing a predetermined voltage level. Thevoltage level provided by such a reference circuit undesirably tends tofluctuate during operation because of temperature variations in theunderlying semiconductor body in which the circuit is integrated.However, in the semiconductor art of analog-to-digital anddigital-to-analog converter circuits, for example, a voltage referenceis desirable which does not fluctuate in voltage level by more thantypically about 0.005 volts or less. Therefore, steps must be taken tostabilize the reference circuit against temperature fluctuations.

In order to obtain a stable reference in either bipolar or complementaryMOS (C-MOS) technology, the industry generally uses voltage referencesutilizing either the voltages associated with reverse breakdownphenomena in Zener diodes or the voltages provided by bandgap referencecircuits. Such bandgap reference circuits are described, for example, inAnalysis and Design of Analog Integrated Circuits, Paul R. Gray andRobert G. Meyer, at pp. 248-261. In N-MOS technology, which uses aP-type semiconductor substrate, none of the above mentioned voltagereferences is feasible. More specifically, Zener diode reverse breakdowncannot easily be used because all PN junctions are designed to withstandthe highest possible reverse voltage available on the semiconductor chipin which the circuits are all integrated; hence these junctions cannotreadily be driven into reverse breakdown. Moreover, known bandgapreference circuits cannot easily be used since they require constantlyforward biased junctions; but, since the P-type substrate in N-MOSintegrated circuits is connected to the most negative potential in thesystem, the requisite constantly forward biased junctions cannot readilyoccur. Thus, to implement either reverse breakdown Zener or bandgapreference circuits in N-MOS technology would require additional costlyfabrication steps, which would impair the economic advantage in N-MOStechnology.

It would therefore be desirable to have a voltage reference circuitwhich can readily be fabricated in N-MOS technology.

SUMMARY OF THE INVENTION

According to the invention, a voltage reference is furnished by thesuitably weighted difference amplification of the voltages developed bytwo junction diodes (D₁, D₂) each of which is periodically pumped in theforward-bias diode direction by a separate clocked current source. Eachsuch current source advantageously includes a capacitor (C₁, C₂) whichis periodically connected to a charging source and which is permanentlyconnected in series with the corresponding diode and a separate MOSdevice (M₂, M₅).

This invention thus involves a voltage reference circuit (10) comprisingfirst and second PN junction diodes (D₁ ; D₂), CHARACTERIZED IN THATeach said diode is separately connected to a different clocked currentsource device (C₁, M₁, M₂, M₃ ; C₂, M₄, M₅, M₆) for supplying current inthe forward-bias diode direction periodically through thecorrespondingly diode, each said diode (D₁ ; D₂) connected to a separateterminal (11; 12) of a weighted difference amplifier (A, C₃, C₄, C₅, C₆)to generate a predetermined weighted difference (aV₁ -bV₂) of theforward voltage drops (V₁ ; V₂) across the diodes (D₁ ; D₂).Advantageously, the circuit is FURTHER CHARACTERIZED IN THAT theweighting factors (a, b) of the weighted difference amplifier aresubstantially in the ratio of: ##EQU1## where V_(xo) is the linearlyextrapolated value of V₁ as a function of temperature from a roomtemperature (T_(x)) to absolute zero; FURTHER CHARACTERIZED IN THAT eachclocked current source device comprises separate capacitor (C₁, C₂), oneof the terminals of each of which is separately connected through thehigh current path of a different MOSFET device (M₁ ; M₄) to a first DCvoltage source terminal (V_(DD)), the gate electrode of each said MOSFETdevice (M₁ ; M₄) being connected to a clocked pulse source terminal (φ);and FURTHER CHARACTERIZED IN THAT each said clocked current sourcedevice further comprises another, separate MOSFET device (M₂ ; M₅) whosehigh current path is separately connected between said one plate of eachcorresponding capacitor (C₁ ; C₂) and a second DC source terminal(V_(SS)), and still further comprises yet another, separate MOSFETdevice (M₃ ; M₆) whose gate electrode is connected to said clocked pulsesource terminal (φ) and whose high current path separately connects theother plate of the capacitor (C₁ ; C₂) to said second DC voltage sourceterminal (V_(SS)).

In a specific embodiment of the invention, each of the diodes (D₁, D₂)is a PN junction semiconductor diode which is periodically pumped by aseparate current source supplying suitable current in the forward biasjunction direction. Each such current source advantageously supplies thedesired current to the corresponding diode by means of the periodicdischarge of a clocked capacitor (C₁, C₂), that is, a capacitor which isperiodically charged by the first and second DC voltage sources (V_(DD),V_(SS)) and which is allowed periodically to discharge through thecorresponding diode. Typically, each diode (D₁, D₂) is connected inseries with an MOS device (M₂, M₅), such as a MOSFET device to whosegate is applied a fixed bias voltage (V_(B)). The periodic charging ofeach capacitor (C₁ and C₂) is typically provided by a pair of separateMOSFET devices (M₁, M₃ and M₄, M₆). One of these MOSFET devices (M₁, M₄)in each pair has its gate electrode connected to a clock pulse sourceterminal (φ) and has its high current (source-drain) path connecting thefirst DC voltage source (V_(DD)) to one terminal of the capacitor (C₁,C₂); each of the other of the MOSFET devices (M₃, M₆) has its gateelectrode connected to the clocked pulse source terminal (φ) and itshigh current path connected between the other terminal of thecorresponding capacitor (C₁, C₂) and ground (V_(SS)) the second DCvoltage source terminal (V_(SS)). The weighted difference amplifier isconveniently provided by an operational amplifier (A) combined with anarrangement of MOS capacitors (C₃, C₄, C₅, C₆) for providing weightingfactors (a, b) to the amplifier (A). All transistors, including those inthe amplifier (A) can be N-MOS devices. In this manner, the circuit ofthis invention for providing a voltage reference can be integrated,together with the circuit to be supplied with this reference, in asingle crystal semiconductive silicon body (same back-gate bias for alltransistors), in accordance with the semiconductor integrated circuitart, in particular such as integrated N-MOS technology.

BRIEF DESCRIPTION OF THE DRAWING

This invention together with its features, objects, and advantages canbe better understood when read in conjunction with the drawing in whichthe FIGURE is a schematic circuit diagram of a semiconductor temperaturestabilized voltage reference circuit 10 in accordance with a specificembodiment of the invention.

DETAILED DESCRIPTION

As shown in the FIGURE, a voltage reference circuit 10 includes adifference amplifier A with an output terminal at which output V_(OUT)is provided for utilization. This amplifier A can conveniently take theform of an operational difference amplifier in N-MOS technology. Theamplifier A has a pair of input terminals labeled + and - to indicatethe respective amplification polarities. A first network for controllinga first PN junction diode D₁ --the first network comprising MOSFETdevices M₁, M₂, and M₃, together with a first MOS capacitor C₁--delivers its output voltage (V_(SS) -V₁) at node 11; and a secondnetwork for controlling a second PN junction diode D₂ --this secondnetwork comprising MOSFET devices M₄, M₅, and M₆, together with a secondMOS capacitor C₂ --delivers its output voltage (V_(SS) -V₂) at node 12.The MOS capacitors C₃, C₄, C₅, and C₆ serve as weighting capacitors forweighting the voltages V₁ and V₂ with input weighting factors a and b inaccordance with the relations:

    V.sub.OUT =aV.sub.1 -bV.sub.2                              (1)

with

    a=C.sub.3 /C.sub.4                                         (2)

and

    b=C.sub.5 (C.sub.3 +C.sub.4)/[C.sub.4 (C.sub.5 +C.sub.6)]  (3)

where an additive offset voltage is neglected in Eq. (1).

The nodes 11 and 12 thus serve as input terminals for the weighteddifference amplifier formed by the amplifier A weighted by thecapacitors C₃, C₄, C₅, and C₆.

The gate electrodes of transistors M₁, M₃, M₄, and M₆ are all connectedto a clock pulse voltage terminal φ which supplies periodic voltagepulses to turn these transistors periodically "on" and "off"; whereasthe gate electrodes of transistors M₂ and M₅ are connected to anintermediate DC voltage bias source V_(B), of voltage leveladvantageously lying between voltages V_(SS) and V_(DD). The actuallevel of V_(B) is selected to make the transistors M₂ and M₅ operate assuitable constant current sources whenever their source-drain voltageexceeds a threshold determined by V_(B), as more fully explained below.

In order to reset the amplifier A, source-drain paths of MOSFETs M₇ andM₈ are connected in parallel, respectively, with the capacitors C₄ andC₆. The gate electrodes of M₇ and M₈ are connected to the clockedvoltage source terminal φ. The MOSFETs M₇ and M₈ thus ensure a periodicdischarge of the node 13 between C₃ and C₄, and the node 14 between C₅and C₆.

Each of the diodes D₁ and D₂ is formed, for example in N-MOS technology,by an N-type localized zone in a P-type semiconductor body. These N-typelocalized zones of the diodes D₁ and D₂ can be formed simultaneouslywith the formation of the source and drain zones of the various(N-channel) MOSFET devices in accordance with standard N-MOS technology;thus, no additional fabrication steps are required for fabricating thesediodes D₁ and D₂. The capacitors C₁ and C₂ are MOS capacitorsadvantageously integrated in the semiconductor body together with thediodes D₁ and D₂ and the MOSFETs M₁, M₂, . . . M₆.

In a typical example in N-MOS implementation, by way of illustration thefollowing approximate values for parameters can be used: V_(DD) =+5 V;ground is zero; V_(SS) =-5 V; the P-type body (substrate) is connectedto V_(SS) ; the pulse height at the clocked terminal φ is +10 V withperiodicity 10 μs; while the remaining parameters are advantageouslyselected in accordance with criteria set forth in the APPENDIX below.The dimensions of the transistors M₁, M₃, M₄, M₆, M₇ and M₈ --all ofwhich function as "on-off" switches--are selected to be sufficient toenable these transistors to switch with sufficiently small delaysconsistent with the rate of the clock φ.

During operation, voltages (V_(SS) -V₁) and (V_(SS) -V₂) are developedat nodes 11 and 12, respectively, as a consequence of the periodiccharging of the capacitors C₁ and C₂, respectively, through thetransistors M₁, M₃, and M₄, M₆, respectively, during the "on" phases ofthe clock φ. These capacitors periodically are discharged, during the"off" phases of M₁ and M₄, both through the diodes D₁ and D₂ and throughthe devices M₂ and M₅, respectively, as more fully described below.

During the "on" phases of the clock φ, the capacitors C₁ and C₂ are bothcharged to a voltage (V_(DD) -V_(SS)) by virtue of the connection of oneterminal of each of these capacitors to V_(SS) through the high current(source-to-drain) path of transistors M₃ and M₆, respectively, and theconnection of the other terminal of each of these capacitors to V_(DD)through the high current path of M₁ and M₄, respectively. In N-MOStechnology, the polarity of resulting charge is positive on theleft-hand terminal of capacitor C₁ and on the right-hand terminal of C₂; that is, this polarity is the same as that of V_(DD).

During the "off" phases of the clock φ, the capacitors C₁ and C₂ slowlydischarge and thereby provide forward current to the diodes D₁ and D₂,respectively. During these discharges, the MOSFETs M₂ and M₅ will remainin saturation so long as the time intervals Δt₁ and Δt₂ are largecompared with the duration of each such "off" phase of φ, where Δt₁ andΔt₂ are given by:

    Δt.sub.1 =(C.sub.1 /I.sub.1)(V.sub.DD -V.sub.SS +V.sub.TH -V.sub.B -V.sub.1)                                                 (4)

    Δt.sub.2 =(C.sub.2 /I.sub.2)(V.sub.DD -V.sub.SS +V.sub.TH -V.sub.B -V.sub.2)                                                 (5)

where I₁ and I₂ are the respective currents through D₁ and D₂ (equal tocurrents through M₂ and M₅), and V_(TH) is the (asumedly equal)threshold voltage of the transistor M₂ or M₅. These conditions on Δt₁and Δt₂ follow from the fact that each of the transistors M₂ and M₅ goesbelow saturation when its drain voltage goes below V_(B) -V_(TH).

The periodicity of φ is, of course, dictated in part by the values ofΔt₁ and Δt₂.

For optimum operation, it is desirable that M₂ and M₅ remain insaturation during every entire "off" phase of the clock φ, so that V₁and V₂ remain substantially constant during every such "off" phase;consequently, the capacitors C₁ and C₂ should be selected to besufficiently large that both Δt₁ and Δt₂, given by Eqs. (4) and (5)above, are greater than the duration of each such "off" phase of theclock φ, advantageously by a factor of at least 2 or 3. In this way,during every "off" phase, the capacitors C₁ and C₂ in series with thetransistors M₂ and M₅, respectively, act as sources of constant forwardcurrent for the diodes D₁ and D₂, respectively, that is, constantcurrents of polarity in the forward biased junction directions of thesediodes.

The magnitude of the desired saturation currents I₁ and I₂ during the"off" phases of the clock φ--that is, during the discharge phases of thecapacitors C₁ and C₂, respectively--will be determined by the respectiveparameters of the transistors, such as structure sizes (channel lengthto width ratios), magnitude of V_(B), doping levels in channels, andsource-to-drain voltage drops. As mentioned above, for advantageousoperation, both these currents I₁ and I₂ should be the "saturation"values; that is, the transistors M₂ and M₅ are operated in theirrespective saturation regions, where the current is relativelyinsensitive to drain-to-source voltage fluctuations within operatinglimits. Thus, during the "off" phases of φ, when the slow discharge ofthe capacitors C₁ and C₂ occurs, these capacitors plus the transistorsM₂ and M₅ act as constant current generators for the diodes D₁ and D₂,respectively.

The corresponding voltages developed across the diodes D₁ and D₂, i.e.,V₁ and V₂, will be the respective characteristic forward bias voltagesof these diodes at their common operating temperature, that is, thetemperature of the semiconductor body in which these diodes areintegrated. These voltages V₁ and V₂ are developed only during the "off"phases of φ; and these voltages are sensed by the amplifier A, whichthereby produces an output voltage V_(OUT), satisfying the relationship:

    V.sub.OUT =aV.sub.1 -bV.sub.2 -V.sub.os                    (6)

where V_(os) is the offset voltage which should be added to Eq. (1), anda and b are the weighting factors given by Eqs. 2 and 3 above.

The voltage V_(OUT) is produced only during the "off" phase of the clockφ. During the "on" phase of this clock φ, the capacitors C₁ and C₂ areboth charged to the voltage V_(DD) -V_(SS), while the voltages at nodes11 and 12 both drop to V_(SS) by virtue of the "on" conditions oftransistors M₃ and M₆. During this "on" phase of the clock φ, the outputof the amplifier therefore drops to the amplifier offset value V_(os).Accordingly, for utilization of the output of the amplifier A in caseswhere a constant, rather than pulsed, reference is desired, a sample andhold circuit means (not shown) can be inserted to control delivery ofthe output V_(OUT) to the utilization circuit (not shown) for utilizingthe voltage reference circuit 10.

If the presence of the offset voltage V_(os) in the output isundesirable, a variety of known offset cancelling schemes can be used,such as charging another capacitor to V_(os) during the "on" phase ofthe clock φ and then connecting this capacitor in series between thenode 14 and the positive input terminal of the amplifier A.

It is further advantageous that the parameters of the transistors M₂ andM₅ be selected such that the saturation currents I₁ and I₂ satisfy:

    I.sub.1 /C.sub.1 =I.sub.2 /C.sub.2                         (7)

In this way, the capacitors C₁ and C₂ discharge at the same rate,thereby ensuring approximate equality of the drain-to-source voltages ofM₂ and M₅, and at the same time ensuring better tracking of thesecurrent sources and hence better efficiency in the development of thevoltages V₁ and V₂. Conveniently, for example, C₁ may be selected to beabout ten times C₂ ; so that I₁ is then about ten times I₂, and thus thechannel width to length ratio of M₂ is then equal to about ten timesthat of M₅. The respective junction areas of diodes D₁ and D₂ areselected in accordance with criteria discussed in the followingAPPENDIX.

APPENDIX

For convenience and definiteness, operation of the first diode network(C₁, D₁, M₂) will be considered alone, and then the combined effect ofthe first and second diode networks (C₁, D₁, M₂ ; and C₂, D₂, M₅) on theamplifier A will be considered.

The voltage V₁ across the diode D₁ is a function of temperature, V₁ =V₁(T), as is the current I₁ =I₁ (T) which is delivered by the currentsource (C₁, M₂). It is well known that:

    I.sub.1 (T)=G(T)e.sup.qV.sbsp.1.sup.(T)/kT                 (8)

and that:

    G(T)=H(T)e.sup.-E.sbsp.g.sup.(T)/kT                        (9)

where q is the electron charge, k is Boltzmann's constant, T is theabsolute temperature, and E_(g) (T) is the bandgap energy of theintrinsic semiconductor at temperature T. Ordinarily, H(T) is of theform:

    H(T)=H.sub.0 (T/T.sub.0).sup.β                        (10)

where H₀ and T₀ are constants, with H₀ proportional to the junction areaof the diode D₁ ; and β is a positive number which is equal to (4-α),where the temperature dependence of the charge carrier mobility in thesemiconductor is given by T⁻α, α is ordinarily equal to about 3/2.

On the other hand, it is also true that the bandgap energy E_(g) (T)varies slowly and almost linearly with temperature T in the neighborhoodof T=300° K., so that a good approximation for E_(g) (T) is given by:

    E.sub.g (T)=E.sub.go -εT                           (11)

where E_(go) is about 1.191 eV for semiconductive silicon, and ε isabout 2.67×10⁻⁴ eV/°K. This quantity E_(go) is the extrapolated bandgapenergy at absolute zero (T=0° K.); but E_(go) is not equal to the actualbandgap energy at any particular temperature because the approximationof Eq. 11 is valid only in the range in temperature of about 200° K. to400° K.

Putting Eq. 11 into Eqs. 9 and 8, it is found that:

    G(T)=H(T)e.sup.-E.sbsp.go.sup./kT e.sup.ε/k        (12)

and

    V.sub.1 (T)=V.sub.go +(kT/q) ln [I.sub.1 (T)/e.sup.ε/k H(T)](13)

with

    V.sub.go =E.sub.go /q.

On the other hand, the current supplied by the current source controlledby load MOSFET M₂ ordinarily satisfies a temperature dependence givenby:

    I.sub.1 (T)=K(T/T.sub.0).sup.-γ                      (14)

where

γ is a constant, and K is proportional to the channel width-to-lengthratio of M₂. Thus, putting Eqs. 10 and 14 into Eq. 13, it follows that:

    V.sub.1 (T)=V.sub.go +(kT/q) ln (BK/T.sup.β+γ)  (15)

with

    B=T.sub.0.sup.β+γ /e.sup.ε/k H.sub.0.

Now, differentiating Eq. 15 with respect to T, the temperaturecoefficient C_(x1) of V₁ (T) evaluated at T=T_(x) =room temperature(300° K.) is: ##EQU2## Thus:

    C.sub.x1 =-[V.sub.xo -V.sub.1 (T.sub.x)]/T.sub.x           (16)

with

    V.sub.xo =V.sub.go +(kT.sub.x /q)(β+γ)          (17)

For silicon, V_(xo) is about 1.23 volts. It should be again noted thatV_(xo) is the linearly extrapolated value of V₁ (T) from T=T_(x) to T=0°K.; that is, V_(xo) is an extrapolation of V₁ (T_(x)) to absolute zeroassuming a straight line relationship of V₁ (T) vs. T, with slope equalto C_(x1). It should also be noted that V_(xo) will be the same for thediode D₁ in the first network (C₁, D₁, M₂) as for the diode D₂ in thesecond network (C₂, D₂, M₅).

Consider a weighted difference of the voltages V₁ (T) and V₂ (T) to formV_(OUT) (T):

    V.sub.OUT (T)=aV.sub.1 (T)-bV.sub.2 (T)                    (18)

For temperature stability of V_(OUT) (T), the temperature derivative ofV₁ (T) at T_(x), the room temperature, is to be set equal to zero:##EQU3## or:

    aC.sub.x1 -bC.sub.x2 =0                                    (20)

For convenience, to solve for the desired values of a and b, set theratio of V_(OUT) (T_(x)) to V_(xo) equal to h:

    h=V.sub.OUT (T.sub.x)/V.sub.xo                             (21)

Evaluate Eq. (18) at T=T_(x) :

    hV.sub.xo =aV.sub.1 (T.sub.x)-bV.sub.2 (T.sub.x)           (22)

Put Eq. (16) and its equivalent counterpart for C_(x2) into Eq. (19):

    -a[V.sub.xo -V.sub.1 (T.sub.x)]/T.sub.x +b[V.sub.xo -V.sub.2 (T.sub.x)]/T.sub.x =0                                     (23)

Solving Eqs. (22) and (23) for the desired values of a and b: ##EQU4##and hence ##EQU5##

Thus, if it is desired to have a preselected value V_(OUT) at T_(x) :first, calculate h=V_(OUT) /V_(xo) ; next, select the parameters for thetwo networks (C₁, D₁, M₂ and C₂, D₂, M₅) such that their roomtemperature diode voltage drops, V₁ (T_(x)) and V₂ (T_(x)), differ by aconvenient nonvanishing value; then, calculate the weighting factors aand b from Eqs. (24a) and (24b); and finally, select the weightingcapacitors C₃, C₄, C₅, and C₆ consistently with Eqs. (2) and (3).

It is thus required that V₁ (T_(x)) be different from V₂ (T_(x)), hencethe first and second diode networks must be constructed differently inone or more parameters of the diodes D₁ and D₂ ; i.e., differingproducts of BK in Eq. 15 for the two networks should be selected, forexample, by selecting differing channel width-to-length ratios of theload transistors M₂ and M₅, while respective junction areas A₁ and A₂ ofdiodes D₁ and D₂ should be selected in accordance with the abovediscussions following Eqs. (14), (15), and (10) as more fully consideredbelow.

It is to be noted that the discussion in connection with above Eqs.(8)-(10) yields:

    V.sub.1 (T.sub.x)-V.sub.2 (T.sub.x)=(kT.sub.x) ln (I.sub.1 A.sub.2 /I.sub.2 A.sub.1)                                                  (26)

where A₁ and A₂ are the junction areas of the diodes D₁ and D₂,respectively; and I₁ and I₂ are the diode currents at room temperatureT_(x). The desirability of current tracking of the two diodes and ofeconomy of semiconductor surface area indicates that for V₁ (T_(x))>V₂(T_(x)) the ratio I₁ A₂ /I₂ A₁ or (I₁ /A₁)/(I₂ /A₂) should be less thanabout 100. On the other hand, kT/q is equal to about 0.026 volts atT=300° K., and ln (100) is equal to about 4.6; thus, V₁ (T_(x))-V₂(T_(x)) should be less than about 0.026×4.6=0.12 volt for a roomtemperature T_(x) =300° K. The voltages V₁ (T_(x)) and V₂ (T_(x)) areboth equal to about 0.6 volt for conveniently designed diodes insilicon, while V_(xo) is equal to about 1.2 volt. Furthermore, both aand b should be less than about 100, for reasons of reasonable matchingand economy of semiconductor area. These considerations impose further,though not too strict, conditions upon the desirable parameters.

As an illustrative example, for a reference V_(OUT) of about 1.2 volt,it is seen from Eq. (21) that h is equal to about unity, so that V₁(T_(x))-V₂ (T_(x)) from Eqs. (24) and (25) should be greater than about0.6/100=0.006 volt, and ln (I₁ A₂ /I₂ A₁) from Eq. (26) should thereforebe greater than about 0.006/0.026=0.23; hence (I₁ A₂ /I₂ A₁) or (I₁/A₁)/(I₂ /A₂) should be greater than antiln (0.23) or about 1.26 at roomtemperature T_(x) =300° K.

Similarly, for a reference V_(OUT) of about 6 volt, h=5; V₁ (T_(x))-V₂(T_(x)) should therefore be greater than about 5×0.6/100=0.030 volt, andln (I₁ A₂ /I₂ A₁) greater than about 0.030/0.026=1.16, and hence (I₁ A₂/I₂ A₁) or (I₁ /A₁)/(I₂ /A₂) should be greater than about 3.2 at roomtemperature T_(x) =300° K.

Although this invention has been described in terms of a specificembodiment, various modification can be made without departing from thescope of the invention. For example, the transistors M₇ and M₈ can beomitted and other means can optionally be supplied for the reset purposeif desired.

What is claimed is:
 1. A voltage reference circuit comprising first andsecond PN junction diodes (D₁ ; D₂), CHARACTERIZED IN THAT each saiddiode is separately connected to a different clocked current sourcearrangement (C₁, M₁, M₂, M₃ ; C₂, M₄, M₅, M₆) for supplying current inthe forward-bias diode direction periodically through the correspondingdiode, and each said diode (D₁ ; D₂) connected to a separate terminal(11; 12) of a weighted difference amplifier (A, C₃, C₄, C₅, C₆) togenerate a predetermined weighted difference (aV₁ -bV₂) of the forwardvoltage drops (V₁ ; V₂) across the diodes (D₁ ; D₂).
 2. A circuitaccording to claim 1 FURTHER CHARACTERIZED IN THAT the weighting factors(a, b) of the weighted difference amplifier are substantially in theratio of: ##EQU6## where V_(xo) is the linearly extrapolated value ofV₁, as a function of temperature, from a room temperature T_(x) toabsolute zero.
 3. A circuit according to claim 1 or 2 FURTHERCHARACTERIZED IN THAT each clocked current source arrangement comprisesa separate capacitor (C₁, C₂) one of the terminals of each of which isseparately connected through the high current path of a different MOSFETdevice (M₁ ; M₄) to a first DC voltage source terminal (V_(DD)), thegate electrode of each said MOSFET device (M₁ ; M₄) being connected to aclock pulse source (φ), and another of the terminals of each capacitor(C₁, C₂) is respectively connected to a different one of said diodes(D₁, D₂).
 4. A circuit according to claim 3 FURTHER CHARACTERIZED INTHAT each said clocked current source arrangement further comprisesanother, separate MOSFET device (M₂ ; M₅) whose high current path isseparately connected between said one plate of each correspondingcapacitor (C₁ ; C₂) and a second DC source terminal (V_(SS)), and stillfurther comprises yet another, MOSFET device (M₃ ; M₆) whose gateelectrode is connected to said clocked pulse source (φ) and whose highcurrent path separately connects the other plate of the capacitor (C₁ ;C₂) to said second DC source terminal (V_(SS)).
 5. Semiconductorapparatus comprising:(a) a weighted difference amplifier having a pairof input terminals (11, 12); (b) a first network for supplying a firstvoltage (V_(SS) -V₁) to one of said input terminals (11), said networkcomprising a first PN junction diode (D₁) integrated in a semiconductorbody and connected in series with a first clocked current arrangementfor periodically forward-biasing the diode (D₁); and (c) a secondnetwork for supplying a second voltage (V_(SS) -V₂) to another of saidinput terminals (12), said second network comprising a second PNjunction diode (D₂) integrated in said semiconductor body and connectedin series with a second clocked current source arrangement forperiodically forward-biasing the second diode (D₂).
 6. Apparatusaccording to claim 5 in which the first and second clocked currentnetworks are connected to a common clock pulse terminal for supplyingclocked pulses to said clocked current arrangements.
 7. Apparatusaccording to claim 5 or 6 in which each said current source arrangementcomprises a separate capacitor (C₁, C₂) in series with a load transistor(M₂, M₅), each of said capacitors (C₁, C₂) being connected respectivelyto a different one of each of said diodes (D₁, D₂).